The present disclosure relates to power amplification circuits.
A power amplification circuit is used in a mobile communication device such as a cellular phone in order to amplify the power of a radio frequency (RF) signal to be transmitted to a base station. A bias circuit is used in such a power amplification circuit. The bias circuit is for supplying a bias current to a power amplification transistor. For example, Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2005-501458 discloses a power amplification circuit that uses a bias circuit formed of a cascode current mirror circuit.
The bias circuit disclosed in Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2005-501458 includes a transistor (Q3) that outputs a bias current from the emitter thereof and a transistor (Q2) that is connected to a ground-side of the transistor (Q3). An amplification transistor (Q1) is charged by the transistor (Q3) and is discharged by the transistor (Q2). The discharging speed of the transistor (Q2) is somewhat higher than or equal to the charging speed of the transistor (Q3) when the output power (input power) is low. On the other hand, as the output power (input power) increases, the discharging speed of the transistor (Q2) becomes lower than the charging speed of the transistor (Q3). Thus, the base voltage of the amplification transistor (Q1) at the time of a high output power increases and linearity of the amplification transistor (Q1) is improved. However, in this bias circuit, current consumption is increased due to a current flowing through the transistor (Q2) at the time of a low output power.